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      A power efficient electronic implant for a visual cortical neuroprosthesis.

      Artificial Organs
      Algorithms, Electric Stimulation, instrumentation, Electrodes, Implanted, Electronics, Medical, Miniaturization, Prostheses and Implants, Signal Processing, Computer-Assisted, Visual Cortex, physiology

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          Abstract

          An integrated microstimulator designed for a cortical visual prosthesis is presented, along with a pixel reordering algorithm, together minimizing the peak total current and voltage required for stimulation of large numbers of electrodes at a high rate. In order to maximize the available voltage for stimulation at a given supply voltage for generating biphasic pulses, the device uses monopolar stimulation, where the return electrode voltage is dynamically varied. Thus, the voltage available for stimulation is maximized, as opposed to the conventional fixed return voltage monopolar approach, and impedance is significantly lower than can be achieved using bipolar stimulation with microelectrodes. This enables the use of a low voltage power supply, minimizing power consumption of the device. An important constraint resulting from this stimulation strategy, however, is that current generation needs to be simultaneous and in-phase for all active parallel channels, imposing heavy stress on the wireless power recovery and regulation circuitry in large electrode count systems such as a visual prosthesis. An ordering algorithm to be implemented in the external controller of the prosthesis is then proposed. Based on the data for each frame of the video signal to be transmitted to the implant, the algorithm minimizes the total generated current standard deviation between time multiplexed stimulations by determining the most appropriate combination of parallel stimulation channels to be activated simultaneously. A stimulator prototype has been implemented in CMOS technology and successfully tested. Execution of the external controller reordering algorithm on an application specific hardware architecture has been verified using a System-On-Chip development platform. A near 75% decrease in the total stimulation current standard deviation was observed with a one-pass algorithm, whereas a recursive variation of the algorithm resulted in a greater than 95% decrease of the same variable.

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