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      Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous integration with Si

      , , , , , , ,
      Applied Physics Letters
      AIP Publishing

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          Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor Applications

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            Nucleation mechanisms and the elimination of misfit dislocations at mismatched interfaces by reduction in growth area

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              GaP-nucleation on exact Si (001) substrates for III/V device integration

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                Author and article information

                Journal
                Applied Physics Letters
                Appl. Phys. Lett.
                AIP Publishing
                0003-6951
                1077-3118
                June 08 2015
                June 08 2015
                : 106
                : 23
                : 233101
                Article
                10.1063/1.4921962
                12a0ef00-1408-4bb5-bc42-fc73efade8a3
                © 2015
                History

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