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      Novel co-design of NAND flash memory and NAND flash controller circuits for sub-30nm low-power high-speed solid-state drives (SSD)

      proceedings-article
      IEEE
      2008 IEEE Symposium on VLSI Circuits
      July 18, 2008 - July 20, 2008

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          Conference
          IEEE
          June 2008
          June 2008
          : 124-125
          Article
          10.1109/VLSIC.2008.4585977
          27f187a0-2eb4-4235-890c-cbdbf524e451
          © 2008
          2008 IEEE Symposium on VLSI Circuits
          Honolulu, HI, USA
          July 18, 2008 - July 20, 2008
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