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PSP: Parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC
Author(s):
K. Rahimunnisa
,
P. Karthigaikumar
,
N Christy
,
S KUmar
,
J Jayakumar
Publication date:
2013
Journal:
Open Computer Science
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Higher order chromatin architecture
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DOI::
10.2478/s13537-013-0112-2
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