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      Formal Verification of SystemC Designs Using a Petri-Net Based Representation

      proceedings-article
      , ,
      IEEE
      2006 Design, Automation and Test in Europe
      April 6, 2006 - April 10, 2006

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          Conference
          IEEE
          2006
          2006
          : 1-6
          Article
          10.1109/DATE.2006.244076
          33a62fe0-53a3-411d-8a52-a03e0a5b9eff
          © 2006
          2006 Design, Automation and Test in Europe
          Munich, Germany
          April 6, 2006 - April 10, 2006
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