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      Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer

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      Journal of Low Power Electronics and Applications
      MDPI AG

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          The Raw microprocessor: a computational fabric for software circuits and general-purpose programs

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            A survey of architectural techniques for improving cache power efficiency

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              An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS

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                Author and article information

                Journal
                Journal of Low Power Electronics and Applications
                JLPEA
                MDPI AG
                2079-9268
                June 2017
                May 29 2017
                : 7
                : 2
                : 14
                Article
                10.3390/jlpea7020014
                43c8a890-77e8-46bf-843f-9ef86931ea42
                © 2017

                https://creativecommons.org/licenses/by/4.0/

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