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      Partial Sums Computation In Polar Codes Decoding

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          Abstract

          Polar codes are the first error-correcting codes to provably achieve the channel capacity but with infinite codelengths. For finite codelengths the existing decoder architectures are limited in working frequency by the partial sums computation unit. We explain in this paper how the partial sums computation can be seen as a matrix multiplication. Then, an efficient hardware implementation of this product is investigated. It has reduced logic resources and interconnections. Formalized architectures, to compute partial sums and to generate the bits of the generator matrix k^n, are presented. The proposed architecture allows removing the multiplexing resources used to assigned to each processing elements the required partial sums.

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          Author and article information

          Journal
          2013-10-07
          2015-01-09
          Article
          1310.1712
          41c4646e-b55e-43e5-891b-4406a93a2130

          http://arxiv.org/licenses/nonexclusive-distrib/1.0/

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          Custom metadata
          Accepted to ISCAS 2015
          cs.AR cs.IT math.IT

          Numerical methods,Information systems & theory,Hardware architecture
          Numerical methods, Information systems & theory, Hardware architecture

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