A 0.039 mm<formula formulatype="inline"><tex Notation="TeX">$^2$</tex> </formula> Inverter-Based 1.82 mW 68.6<formula formulatype="inline"><tex Notation="TeX">$~$</tex> </formula>dB-SNDR 10 MHz-BW CT-<formula formulatype="inline"><tex Notation="TeX">$\Sigma\Delta$</tex> </formula>-ADC in 65 nm CMOS Using Power- and Area-Efficient Design Techniques

Zeller, Sebastian; Muenker, Christian; Weigel, Robert; Ussmueller, Ussmueller

doi:10.1109/JSSC.2014.2321063

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A 0.039 mm<formula formulatype="inline"><tex Notation="TeX">$^2$</tex> </formula> Inverter-Based 1.82 mW 68.6<formula formulatype="inline"><tex Notation="TeX">$~$</tex> </formula>dB-SNDR 10 MHz-BW CT-<formula formulatype="inline"><tex Notation="TeX">$\Sigma\Delta$</tex> </formula>-ADC in 65 nm CMOS Using Power- and Area-Efficient Design Techniques

Author(s): Sebastian Zeller , Christian Muenker , Robert Weigel , Ussmueller Ussmueller

Publication date (Print): July 2014

Journal: IEEE Journal of Solid-State Circuits

Publisher: Institute of Electrical and Electronics Engineers (IEEE)

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Journal

Title: IEEE Journal of Solid-State Circuits

Abbreviated Title: IEEE J. Solid-State Circuits

Publisher: Institute of Electrical and Electronics Engineers (IEEE)

ISSN (Print): 0018-9200

ISSN (Electronic): 1558-173X

Publication date Created: July 2014

Publication date (Print): July 2014

Volume: 49

Issue: 7

Pages: 1548-1560

Article

DOI: 10.1109/JSSC.2014.2321063

SO-VID: 54c5ab0a-a8f7-47f8-ac5a-aa63dd9c2006

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