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      Electrical characteristics of field-effect transistors based on indium arsenide nanowire thinner than 10 nm

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          Nanowire transistors without junctions.

          All existing transistors are based on the use of semiconductor junctions formed by introducing dopant atoms into the semiconductor material. As the distance between junctions in modern devices drops below 10 nm, extraordinarily high doping concentration gradients become necessary. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms, such junctions represent an increasingly difficult fabrication challenge for the semiconductor industry. Here, we propose and demonstrate a new type of transistor in which there are no junctions and no doping concentration gradients. These devices have full CMOS functionality and are made using silicon nanowires. They have near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.
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            Is Open Access

            Ultrathin compound semiconductor on insulator layers for high performance nanoscale transistors

            Over the past several years, the inherent scaling limitations of electron devices have fueled the exploration of high carrier mobility semiconductors as a Si replacement to further enhance the device performance. In particular, compound semiconductors heterogeneously integrated on Si substrates have been actively studied, combining the high mobility of III-V semiconductors and the well-established, low cost processing of Si technology. This integration, however, presents significant challenges. Conventionally, heteroepitaxial growth of complex multilayers on Si has been explored. Besides complexity, high defect densities and junction leakage currents present limitations in the approach. Motivated by this challenge, here we utilize an epitaxial transfer method for the integration of ultrathin layers of single-crystalline InAs on Si/SiO2 substrates. As a parallel to silicon-on-insulator (SOI) technology14,we use the abbreviation "XOI" to represent our compound semiconductor-on-insulator platform. Through experiments and simulation, the electrical properties of InAs XOI transistors are explored, elucidating the critical role of quantum confinement in the transport properties of ultrathin XOI layers. Importantly, a high quality InAs/dielectric interface is obtained by the use of a novel thermally grown interfacial InAsOx layer (~1 nm thick). The fabricated FETs exhibit an impressive peak transconductance of ~1.6 mS/{\mu}m at VDS=0.5V with ON/OFF current ratio of greater than 10,000 and a subthreshold swing of 107-150 mV/decade for a channel length of ~0.5 {\mu}m.
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              Fermi Level Position at Semiconductor Surfaces

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                Author and article information

                Journal
                Applied Physics Letters
                Appl. Phys. Lett.
                AIP Publishing
                0003-6951
                1077-3118
                October 06 2014
                October 06 2014
                : 105
                : 14
                : 143101
                Affiliations
                [1 ]Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871, China
                [2 ]State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China
                Article
                10.1063/1.4897496
                585bb98c-445e-478e-84fd-f0bd959ea406
                © 2014
                History

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