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      Miniaturization of CMOS

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          Abstract

          When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

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          Most cited references243

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          Cramming More Components Onto Integrated Circuits

          G.E. Moore (1998)
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            Field-effect transistors built from all two-dimensional material components.

            We demonstrate field-effect transistors using heterogeneously stacked two-dimensional materials for all of the components, including the semiconductor, insulator, and metal layers. Specifically, MoS2 is used as the active channel material, hexagonal-BN as the top-gate dielectric, and graphene as the source/drain and the top-gate contacts. This transistor exhibits n-type behavior with an ON/OFF current ratio of >10(6), and an electron mobility of ∼33 cm(2)/V·s. Uniquely, the mobility does not degrade at high gate voltages, presenting an important advantage over conventional Si transistors where enhanced surface roughness scattering severely reduces carrier mobilities at high gate-fields. A WSe2-MoS2 diode with graphene contacts is also demonstrated. The diode exhibits excellent rectification behavior and a low reverse bias current, suggesting high quality interfaces between the stacked layers. In this work, all interfaces are based on van der Waals bonding, presenting a unique device architecture where crystalline, layered materials with atomically uniform thicknesses are stacked on demand, without the lattice parameter constraints. The results demonstrate the promise of using an all-layered material system for future electronic applications.
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              Anisotropic Etching of Crystalline Silicon in Alkaline Solutions

              R H Seidel (1990)
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                Author and article information

                Journal
                Micromachines (Basel)
                Micromachines (Basel)
                micromachines
                Micromachines
                MDPI
                2072-666X
                30 April 2019
                May 2019
                : 10
                : 5
                : 293
                Affiliations
                [1 ]Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; hexiaobin@ 123456ime.ac.cn (X.H.); zhangqingzhu@ 123456ime.ac.cn (Q.Z.); liujinbiao@ 123456ime.ac.cn (J.L.); xiangjinjuan@ 123456ime.ac.cn (J.X.); kongzhenzhen@ 123456ime.ac.cn (Z.K.); xiongwenjuan@ 123456ime.ac.cn (W.X.); lijunjie@ 123456ime.ac.cn (J.L.); gaojianfeng@ 123456ime.ac.cn (J.G.); yanghong@ 123456ime.ac.cn (H.Y.); gushihai@ 123456ime.ac.cn (S.G.); zhaoxuewei@ 123456ime.ac.cn (X.Z.); duyong@ 123456ime.ac.cn (Y.D.); yujiahan@ 123456ime.ac.cn (J.Y.)
                [2 ]Microelectronics Institute, University of Chinese Academy of Sciences, Beijing 100049, China
                [3 ]Department of Electronics Design, Mid Sweden University, Holmgatan 10, 85170 Sundsvall, Sweden
                [4 ]State Key Laboratory of Advanced Materials for Smart Sensing, General Research Institute for Nonferrous Metals, Beijing 100088, China
                [5 ]Fert Beijing Institute, Big Data Brain Computing (BDBC), Beihang University, Beijing 100191, China; cuihusan@ 123456ime.ac.cn
                [6 ]School of Artificial Intelligence, University of Chinese Academy of Sciences, Beijing 100049, China
                [7 ]School of Microelectronics, University of Science and Technology of China, Anhui 230026, China
                Author notes
                [* ]Correspondence: rad@ 123456ime.ac.cn (H.H.R.); wangguilei@ 123456ime.ac.cn (G.W.); Tel.: +86-010-8299-5793 (G.W.)
                [†]

                The authors have equally contributed in this article.

                Author information
                https://orcid.org/0000-0003-2860-5901
                Article
                micromachines-10-00293
                10.3390/mi10050293
                6563067
                31052223
                5fa92cc6-2197-451d-9398-f25e44dbf812
                © 2019 by the authors.

                Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license ( http://creativecommons.org/licenses/by/4.0/).

                History
                : 03 March 2019
                : 11 April 2019
                Categories
                Review

                finfets,cmos,device processing,integrated circuits
                finfets, cmos, device processing, integrated circuits

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