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      Method and Implementation of High-speed Digital Sampling Technology Based on Impulse Radar Signal

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          Abstract

          A High-speed digital sampling technology suitable for periodical impulse radar signal is proposed in this paper. One bit high-speed quantize is constructed by differential comparator in FPGA. Time-interleaved digital sampling and buffer encoding are used to one bit stream based on the internal multi-phase clock of FPGA, to achieve sampling rate higher than 1 GHz. High speed digital sampling is realized by the accumulation of one bit sampling data with different comparison levels. An 8 bit, 1.6 GHz ADC based on the proposed method is realized on XC2V3000 Xilinx’s FPGA, which is successfully applied in GPR. The proposed method has the advantages of low cost and power consumption as compared with real sampling, and exhibits higher efficiency as compared with equivalent sampling.

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          Author and article information

          Journal
          Journal of Radars
          Chinese Academy of Sciences
          01 June 2012
          : 1
          : 2
          : 136-142
          Affiliations
          [1 ] Key Laboratory of Electromagnetic Radiation and Detection Technology, the Institute of Electronics, Chinese Academy of Science
          Article
          d99a850ee7d3494c8baa2fda7adaff28
          10.3724/SP.J.1300.2012.20022

          This work is licensed under a Creative Commons Attribution 4.0 Unported License. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/

          Categories
          Technology (General)
          T1-995

          Remote sensing, Electrical engineering

          One bit quantize, Digital sampling, FPGA, Compare level

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