Third International Workshop on Verification and Evaluation of Computer and Communication Systems (VECoS 2009) (VECOS)
Verification and Evaluation of Computer and Communication Systems (VECoS 2009)
2-3 July 2009
The work presented in this paper is part of a project that aims to develop of a new approach to time-constrained system verification based on UML. In fact, being relatively easy to learn and use, UML is very popular, unlike formal methods. Nevertheless, formal models provide developers with several advantages: they can be used for activities, such as properties verification, which are crucial for critical system development. Such activities are less effective when carried out on UML models. Also, because UML semantics is informal, the automatic verification of UML models is directly unfeasible. In this paper, we propose a new verification approach that takes advantage of UML Statecharts model to implement a new technique based on both Timed Automata Observers and model checking. The contributions of the paper are the definition of new time constraints (properties) taxonomy and the definition of a Statecharts patterns’ base. These patterns are then translated to Timed Automata Observers. The obtained observers are synchronized with the system specification, thus reducing the verification task to a reachability analysis.