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      Evaluation of DVFS techniques on modern HPC processors and accelerators for energy-aware applications

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          Abstract

          Energy efficiency is becoming increasingly important for computing systems, in particular for large scale HPC facilities. In this work we evaluate, from an user perspective, the use of Dynamic Voltage and Frequency Scaling (DVFS) techniques, assisted by the power and energy monitoring capabilities of modern processors in order to tune applications for energy efficiency. We run selected kernels and a full HPC application on two high-end processors widely used in the HPC context, namely an NVIDIA K80 GPU and an Intel Haswell CPU. We evaluate the available trade-offs between energy-to-solution and time-to-solution, attempting a function-by-function frequency tuning. We finally estimate the benefits obtainable running the full code on a HPC multi-GPU node, with respect to default clock frequency governors. We instrument our code to accurately monitor power consumption and execution time without the need of any additional hardware, and we enable it to change CPUs and GPUs clock frequencies while running. We analyze our results on the different architectures using a simple energy-performance model, and derive a number of energy saving strategies which can be easily adopted on recent high-end HPC systems for generic applications.

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          Most cited references 33

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          Modeling Dynamic Architectures Using Dy-BIP

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              An Energy Efficiency Feature Survey of the Intel Haswell Processor

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                Author and article information

                Journal
                2017-03-08
                10.1002/cpe.4143
                1703.02788

                http://arxiv.org/licenses/nonexclusive-distrib/1.0/

                Custom metadata
                cs.DC cs.PF

                Performance, Systems & Control, Networking & Internet architecture

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