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      Low Cost Interconnected Architecture for the Hardware Spiking Neural Networks

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          Abstract

          A novel low cost interconnected architecture (LCIA) is proposed in this paper, which is an efficient solution for the neuron interconnections for the hardware spiking neural networks (SNNs). It is based on an all-to-all connection that takes each paired input and output nodes of multi-layer SNNs as the source and destination of connections. The aim is to maintain an efficient routing performance under low hardware overhead. A Networks-on-Chip (NoC) router is proposed as the fundamental component of the LCIA, where an effective scheduler is designed to address the traffic challenge due to irregular spikes. The router can find requests rapidly, make the arbitration decision promptly, and provide equal services to different network traffic requests. Experimental results show that the LCIA can manage the intercommunication of the multi-layer neural networks efficiently and have a low hardware overhead which can maintain the scalability of hardware SNNs.

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          Most cited references 55

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          Networks on chips: a new SoC paradigm

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            Overview of the SpiNNaker System Architecture

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              TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip

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                Author and article information

                Contributors
                Journal
                Front Neurosci
                Front Neurosci
                Front. Neurosci.
                Frontiers in Neuroscience
                Frontiers Media S.A.
                1662-4548
                1662-453X
                21 November 2018
                2018
                : 12
                Affiliations
                [1] 1Faculty of Electronic Engineering, Guangxi Normal University , Guilin, China
                [2] 2School of Computing, Engineering and Intelligent Systems, University of Ulster , Londonderry, United Kingdom
                [3] 3Management Science and Business Economics Group, Business School, University of Edinburgh , Edinburgh, United Kingdom
                [4] 4College of Mathematics and Informatics, Fujian Normal University , Fuzhou, China
                Author notes

                Edited by: Frank Markus Klefenz, Fraunhofer-Institut für Digitale Medientechnologie IDMT, Germany

                Reviewed by: Horacio Rostro Gonzalez, Universidad de Guanajuato, Mexico; Dongwei Hu, The University of Manchester, United Kingdom

                *Correspondence: Junxiu Liu, j.liu@ 123456ieee.org

                This article was submitted to Neuromorphic Engineering, a section of the journal Frontiers in Neuroscience

                Article
                10.3389/fnins.2018.00857
                6258738
                8bef98fa-4236-47df-a6e0-17e298f3e463
                Copyright © 2018 Luo, Wan, Liu, Harkin, McDaid, Cao and Ding.

                This is an open-access article distributed under the terms of the Creative Commons Attribution License (CC BY). The use, distribution or reproduction in other forums is permitted, provided the original author(s) and the copyright owner(s) are credited and that the original publication in this journal is cited, in accordance with accepted academic practice. No use, distribution or reproduction is permitted which does not comply with these terms.

                Page count
                Figures: 12, Tables: 2, Equations: 0, References: 63, Pages: 14, Words: 0
                Funding
                Funded by: National Natural Science Foundation of China 10.13039/501100001809
                Award ID: 61603104
                Award ID: 61801131
                Funded by: Natural Science Foundation of Guangxi Province 10.13039/501100004607
                Award ID: 2016GXNSFCA380017
                Award ID: 2017GXNSFAA198180
                Categories
                Neuroscience
                Original Research

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