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      Impact of oxidation and reduction annealing on the electrical properties of Ge/La 2O 3/ZrO 2 gate stacks

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          Highlights

          ► Ge surface passivation by scalable multilayer of La 2O 3/ZrO 2. ► La x Ge y O z interfacial layers thickness controllable by oxidation time. ► Forming gas annealing improves D it down to 3 × 10 11 eV −1 cm −2 in presence of La x Ge y O z interlayer. ► Trade-off between interface trap density and equivalent oxide thickness.

          Abstract

          The paper addresses the passivation of Germanium surfaces by using layered La 2O 3/ZrO 2 high- k dielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing ambient during thermal post treatment in presence of thin Pt cap layers are demonstrated. The results suggest the formation of thin intermixed La x Ge y O z interfacial layers with thicknesses controllable by oxidation time. This formation is further investigated by XPS, EDX/EELS and TEM analysis. An additional reduction annealing treatment further improves the electrical properties of the gate dielectrics in contact with the Ge substrate. As a result low interface trap densities on (1 0 0) Ge down to 3 × 10 11 eV −1 cm −2 are demonstrated. The formation of the high- k La x Ge y O z layer is in agreement with the oxide densification theory and may explain the improved interface trap densities. The scaling potential of the respective layered gate dielectrics used in Ge-based MOS-based device structures to EOT of 1.2 nm or below is discussed. A trade-off between improved interface trap density and a lowered equivalent oxide thickness is found.

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          The Binary Rare Earth Oxides.

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            Effective electrical passivation of Ge(100) for high-k gate dielectric layers using germanium oxide

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              Ultimate Scaling of CMOS Logic Devices with Ge and III–V Materials

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                Author and article information

                Journal
                Solid State Electron
                Solid State Electron
                Solid-State Electronics
                Pergamon Press
                0038-1101
                1 August 2012
                August 2012
                : 74
                : 5
                : 7-12
                Affiliations
                [a ]Integrated Devices and Circuits, KTH Royal Institute of Technology, School of ICT, Stockholm, Sweden
                [b ]University Service Center for TEM, Vienna University of Technology, Vienna, Austria
                [c ]Institute for Solid State Electronics, Vienna University of Technology, Vienna, Austria
                Author notes
                [* ]Corresponding author. chenkel@ 123456kth.se
                Article
                SSE6016
                10.1016/j.sse.2012.04.004
                3587347
                23483756
                9123e48a-403b-4e68-86e5-f6c991e972f3
                © 2012 Elsevier Ltd.

                This document may be redistributed and reused, subject to certain conditions.

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                Electrical engineering
                germanate,la2o3,high-k,germanium,annealing,oxidation,zro2
                Electrical engineering
                germanate, la2o3, high-k, germanium, annealing, oxidation, zro2

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