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Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream
Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard
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Author(s):
Francisco Cardells-Tormo
,
Javier Valls-Coquillat
,
Vicenc Almenar-Terre
,
Vicente Torres-Carot
Publication date
(Online):
August 16 2002
Publisher:
Springer Berlin Heidelberg
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Value-based Healthcare
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The CORDIC Trigonometric Computing Technique
Jack Volder
(1959)
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A digital frequency synthesizer
J. Tierney
,
B. Gold
,
C Rader
(1971)
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A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range
A.N. Willson
,
A.Y. Kwentus
,
A. Madisetti
(1999)
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Book Chapter
Publication date (Print):
2002
Publication date (Online):
August 16 2002
Pages
: 102-111
DOI:
10.1007/3-540-46117-5_12
SO-VID:
d6ede158-c615-42f3-84b0-b9cbf3278aee
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Book chapters
pp. 1
The Age of Adaptive Computing Is Here
pp. 4
Disruptive Trends by Data-Stream-Based Computing
pp. 5
Multithreading for Logic-Centric Systems
pp. 15
Fast Prototyping with Co-operation of Simulation and Emulation
pp. 26
How Fast Is Rapid FPGA-based Prototyping: Lessons and Challenges from the Digital TV Design Prototyping Project
pp. 36
Implementing Asynchronous Circuits on LUT Based FPGAs
pp. 47
A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations
pp. 59
Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems
pp. 69
iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications
pp. 79
Field-Programmable Custom Computing Machines - A Taxonomy -
pp. 89
Embedded Reconfigurable Logic Core for DSP Applications
pp. 102
Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard
pp. 112
FPGA QAM Demodulator Design
pp. 122
Analytical Framework for Switch Block Design
pp. 132
Modular, Fabric-Specific Synthesis for Programmable Architectures
pp. 142
On Optimum Designs of Universal Switch Blocks
pp. 152
Improved Functional Simulation of Dynamically Reconfigurable Logic
pp. 162
Run-Time Reconfiguration to Check Temperature in Custom Computers: An Application of JBits Technology
pp. 171
Dynamic Reconfiguration in Mobile Systems
pp. 182
Using PARBIT to Implement Partial Run-Time Reconfigurable Systems
pp. 192
Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAs
pp. 202
Speech Recognition on an FPGA Using Discrete and Continuous Hidden Markov Models
pp. 212
FPGA Implementation of the Wavelet Packet Transform for High Speed Communications
pp. 222
A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBits™
pp. 232
Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices
pp. 242
Rapid and Reliable Routability Estimation for FPGAs
pp. 253
Integrated Iterative Approach to FPGA Placement
pp. 263
TDR: A Distributed-Memory Parallel Routing Algorithm for FPGAs
pp. 271
High-Level Partitioning of Digital Systems Based on Dynamically Reconfigurable Devices
pp. 281
High Speed Homology Search Using Run-Time Reconfiguration
pp. 292
Partially Reconfigurable Cores for Xilinx Virtex
pp. 312
A Flexible Power Model for FPGAs
pp. 322
A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs
pp. 332
Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor
pp. 340
A Tool for Activity Estimation in FPGAs
pp. 350
FSM Decomposition for Low Power in FPGA
pp. 360
Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search
pp. 370
A Prolog-Based Hardware Development Environment
pp. 381
Fly — A Modifiable Hardware Compiler
pp. 391
Challenges and Opportunities for FPGA Platforms
pp. 393
Design and Implementation of FPGA Circuits for High Speed Network Monitors
pp. 414
Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques
pp. 424
Field-Programmable Analog Arrays: A Floating—Gate Approach
pp. 434
A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model
pp. 444
A Framework for Teaching (Re)Configurable Architectures in Student Projects
pp. 452
Specialized Hardware for Deep Network Packet Filtering
pp. 462
Implementation of a Successive Erasure BCH (16,7,6) Decoder and Performance Simulation by Rapid Prototyping
pp. 472
Fast RNS FPL-based Communications Receiver Design and Implementation
pp. 482
UltraSONIC: A Reconfigurable Architecture for Video Image Processing
pp. 492
Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA
pp. 503
Implementation of the JPEG 2000 Standard on a Virtex 1000 FPGA
pp. 513
Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices
pp. 523
Automating Customisation of Floating-Point Designs
pp. 534
Energy-Efficient Matrix Multiplication on FPGAs
pp. 545
Run-Time Adaptive Flexible Instruction Processors
pp. 556
DARP — A Digital Audio Reconfigurable Processor
pp. 567
System-Level Modelling for Performance Estimation of Reconfigurable Coprocessors
pp. 577
An FPGA Based SHA-256 Processor
pp. 586
Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension
pp. 596
On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs
pp. 607
Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs
pp. 616
Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs
pp. 627
Logarithmic Number System and Floating-Point Arithmetics on FPGA
pp. 637
Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture
pp. 647
Morphable Multipliers
pp. 657
A Library of Parameterized Floating-Point Modules and Their Use
pp. 667
Wordlength as an Architectural Parameter for Reconfigurable Computing Devices
pp. 677
An Enhanced POLIS Framework for Fast Exploration and Implementation of I/O Subsystems on CSoC Platforms
pp. 687
Introducing ReConfigME: An Operating System for Reconfigurable Computing
pp. 698
Efficient Metacomputation Using Self-Reconfiguration
pp. 710
An FPGA Co-processor for Real-Time Visual Tracking
pp. 720
Implementation of 3-D Adaptive LUM Smoother in Reconfigurable Hardware
pp. 730
Custom Coprocessor Based Matrix Algorithms for Image and Signal Processing
pp. 740
Parallel FPGA Implementation of the Split and Merge Discrete Wavelet Transform
pp. 750
Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2m)
pp. 760
6.78 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm
pp. 770
Rijndael Cryptographic Engine on the UltraSONIC Reconfigurable Platform
pp. 780
A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation
pp. 790
Creating a World of Smart Re-configurable Devices
pp. 795
Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs
pp. 806
Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System
pp. 816
The Case for Fine-Grained Re-configurable Architectures: An Analysis of Conceived Performance
pp. 826
An FPGA Implementation of a Multi-comparand Multi-search Associative Processor
pp. 836
AES Implementation on FPGA: Time - Flexibility Tradeoff
pp. 845
An FPGA Implementation of the Linear Cryptanalysis
pp. 853
Compiling Application-Specific Hardware
pp. 864
XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture
pp. 875
Sea Cucumber: A Synthesizing Compiler for FPGAs
pp. 886
Practical Considerations in the Synthesis of High Performance Digital Filters for Implementation on FPGAs
pp. 897
Low Power High Speed Algebraic Integer Frequency Sampling Filters Using FPLDs
pp. 905
High Performance Quadrature Digital Mixers for FPGAs
pp. 915
HAGAR: Efficient Multi-context Graph Processors
pp. 925
Scalable Implementation of the Discrete Element Method on a Reconfigurable Computing Platform
pp. 935
On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach
pp. 945
REFLIX: A Processor Core for Reactive Embedded Applications
pp. 955
Factors Influencing the Performance of a CPU-RFU Hybrid Architecture
pp. 966
Implementing Converters in FPLD
pp. 976
A Quantitative Understanding of the Performance of Reconfigurable Coprocessors
pp. 987
Integration of Reconfigurable Hardware into System-Level Design
pp. 997
A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures
pp. 1007
The Integration of SystemC and Hardware-Assisted Verification
pp. 1017
Using Design Hierarchy to Improve Quality of Results in FPGAs
pp. 1027
Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations
pp. 1037
A General Hardware Design Model for Multicontext FPGAs
pp. 1048
Dynamically Reconfigurable Hardware — A New Perspective for Neural Network Implementations
pp. 1058
A Compilation Framework for a Dynamically Reconfigurable Architecture
pp. 1068
Data Dependent Circuit for Subgraph Isomorphism Problem
pp. 1072
Exploration of Design Space in ECDSA
pp. 1076
2D and 3D Computer Graphics Algorithms under MORPHOSYS
pp. 1080
A HIPERLAN/2 — IEEE 802.11a Reconfigurable System-on-Chip
pp. 1084
SoftTOTEM: An FPGA Implementation of the TOTEM Parallel Processor
pp. 1088
Real-Time Medical Diagnosis on a Multiple FPGA-based System
pp. 1092
Threshold Element-Based Symmetric Function Generators and Their Functional Extension
pp. 1097
Hardware Implementation of a Multiuser Detection Scheme Based on Recurrent Neural Networks
pp. 1101
Building Custom FIR Filters Using System Generator
pp. 1105
SoC Based Low Cost Design of Digital Audio Broadcasting Transport Network Applications
pp. 1110
Dynamic Constant Coefficient Convolvers Implemented in FPGAs
pp. 1114
VIZARD II: An FPGA-based Interactive Volume Rendering System
pp. 1118
RHiNET/NI: A Reconfigurable Network Interface for Cluster Computing
pp. 1122
General Purpose Prototyping Platform for Data-Processor Research and Development
pp. 1126
High Speed Computation of Three Dimensional Cellular Automata with FPGA
pp. 1131
SOPC-based Embedded Smart Strain Gage Sensor
pp. 1135
Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications
pp. 1139
An FPGA-based Node Controller for a High Capacity WDM Optical Packet Network
pp. 1144
FPGA and Mixed FPGA-DSP Implementations of Electrical Drive Algorithms
pp. 1148
Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer
pp. 1152
A Novel Watermarking Technique for LUT Based FPGA Designs
pp. 1156
Implementing CSAT Local Search on FPGAs
pp. 1160
A Reconfigurable Processor Architecture
pp. 1164
A Reconfigurable System-on-Chip-Based Fast EDM Process Monitor
pp. 1168
Gene Matching Using JBits
pp. 1172
Massively Parallel/Reconfigurable Emulation Model for the D-algorithm
pp. 1177
A Placement/Routing Approach for FPGA Accelerators
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