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      Leakage Minimization Technique for Nanoscale CMOS VLSI

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          Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

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            Variable supply-voltage scheme for low-power high-speed CMOS digital design

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              Leakage power analysis and reduction: models, estimation and tools

                Author and article information

                Journal
                IEEE Design & Test of Computers
                IEEE Des. Test. Comput.
                Institute of Electrical and Electronics Engineers (IEEE)
                0740-7475
                April 2007
                April 2007
                : 24
                : 4
                : 322-330
                Article
                10.1109/MDT.2007.111
                df74db1d-b957-430c-8ee0-81efa579da20
                © 2007
                History

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