Article title: Increased Efficiency of a Current Compensating Load Modulation Based MMIC Doherty Power Amplifier Design In 0.25m GaAs pHEMT Technology Authors: Seyedehmarzieh Rouhani[1],

73225777 Abstract In this work, a premise is applied to the conventional load modulation equation of Doherty power amplifier (DPA) in 0.25  m GaAs pHEMT technology to compensate output impedance of main amplifier ( n Z ) variation, even in low power region. Using this modified modulation leads to the DPA’s power added efficiency (PAE) increase in comparison by the case in which the load modulation revision is ignored, which is also designed in this paper. Second harmonic rejection networks are also added to both designs to play their roles as to efficiency increase. By doing so, the revised load modulation based DPA has the maximum PAE of 39.6%, maximum output power ( ou t P ) of 31.61dBm, at 8 GHz. Simulation results of this DPA in higher harmonics indicate the designed DPA has the minimum second and third harmonics power of -51.7 dBm and -80 dBm, respectively. For the sake of linearity evaluation, it is depicted that 1dB-power gain compression has not occurred in the input power ( i n P ) range in which the proposed


Introduction
The galloping rate of progress in global wireless communication based on which the outermost parts of the world are in contact needs high efficient transceivers by which the demand of portable devices assigned for the mass communication can be met [1][2][3][4][5]. Power amplifiers as subsystems in transceivers always have been in great interest of research [6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25] due to their influence on the efficiency and linearity of whole systems. There is a plethora of novel structures and models proposed to develop PA's efficiency and linearity, such as envelope tracking [26], out-phasing [27], class E and class F PAs [11,28], DPA [29], to name but a few. Among them, DPA has received dramatic acceptance due to its compatibility to deal with the increased PAPR signals [29]. The main concept of DPA is grounded on its load modulation [29], which is done by a 4  transmission line (TL). Many designers have used the Doherty technique to present high-efficiency performance in different technologies in which their proposed PAs were simulated or manufactured [30][31][32][33]. Still, there is a delicate point that should be noticed, and this fact is that ii respectively. At first, it is assumed that there is a linear equation between them (see Eq.2), then the design will be done under these premises. At this point, if the efficiency becomes considerably better than that of the conventional load modulation based design, these assumptions will be accepted. Otherwise, those premises will be changed, and non-linear equations between the parameters mentioned above will be set. The following relations show the procedure of making some changes in the conventional load modulation equation.
At first, we assume: According to load-pull simulation results, at high power region After some simplification, we have: From microwave concepts and principle [34], we know: Here to compensate for the varied Z . If the variation in voltage and current with power (due to impedance variation) is rewritten with  the Eq.6 changes as follows: In conventional DPA, it was assumed that in the low-power region reflection coefficient is equal by zero ( ii ratio discussed in the next section. Fig2. Schematic of the conventional load modulation based DPA (the elements in the grey boxes are the last and the first elements of OMN and IMN of first and second stages PAs, which are merged together in circuit's layout, and the exact amount of all elements is provided in Appendix).

Size selection
There are several choices by which the desired   ' aux main ii ratio can be satisfied. The confining factor for picking the proper one is the stability of the circuit [35]. In the technology this work is designed, the bigger transistor has the stabilizer network with less power gain degradation, a parallel RC network whose capacitance is more, can be utilized. According to this point, the biggest size transistor is chosen, which is then the size of auxiliary ones will be set proportionally to satisfy the   ' aux main ii ratio condition. It should be noticed that, according to [36], instability before 1 GHz for 8 150 m   -transistor can be ignored. Fig.3 indicates the effect of the transistor's size and its stability by using a stabilizer network. Fig3. Stability of the largest and the smallest transistors in 0.25µm pHEMT GaAs technology with stabilizer networks for each one.

Bias consideration
According to the concept of IP3, in multi-stage structures, designers should take more care about the linearity of the last stages [35]. Therefore, in this work, the first stage of aux PA is biased as a deep class C PA while the second one is designed in a soft class C PA. In the main path, both gate stages' biases are set the same because their inherent behavior is linear.

Phase consideration
In a conventional DPA configuration, a 4  TL is put at the input of auxiliary way to compensate for the added 90  phase in the main path of amplification due to the presence of a 4  TL contributing to the load modulation [29]. This phase compensation can be done in matching networks of main PA , no matter in input or inter-stage or output stage matching networks (IMNs, ISMNs, OMNs). Considering the amount of phase should be compensated with matching equation in MNs designing as discussed in [37] leads to circuit and layout's more simplicity. In this work, this extra 90  phase is split into IMNs, ISMNs, OMNs, and they are all optimized to present maximum power and 90  desired phase when aux PA is active.

Input power divider
For the sake of a simple phase difference compensation, the signal path from input to the first stage of each of main PA and aux PA should be equilibrium. Consequently, a symmetric lumped-element Wilkinson power divider with two precisely similar parallel second-harmonic rejection networks on each branch is used. This power divider delivers the maximum power of 11.5 dBm to each of the amplification paths. Fig.4 indicates the performance of this divider. Fig4. Delivered power to both paths of amplification by Wilkinson power divider.

Performance comparison with the conventional load modulation based design
This work is designed grounded on a premise, which is made to develop load modulation, now it is mandatory to scrutinize what will be the result of DPA designing if That slope modification, which leads to PAE increase, cannot be seen in the conventional modulation based design, and it means that in that case, the load modulation is not correctly done. Fig.6 and Fig.7  ii factor, as it did in conventional DPA, doesn't necessarily lead to reach the best possible performance of PA. It is worthwhile to notice that CCLM cannot be generalized with linear assumptions to all other technologies; according to , out main Z trajectory, designers should take the appropriate strategy for their design. For the sake of linearity assessment, power gain compression of both DPAs is depicted in Fig.8 in which no more than 1 dB gain compression has occurred. Table 1 represents the performances of both designs.

Harmonic consideration
Higher-order harmonic rejection is a method to increase the efficiency of PAs. For the sake of making the efficiency of PA raised as much as possible, it is mandatory to take action against the undesired harmonics. The second harmonics of in P can be rejected if an adequately large impedance is in PA input at that harmonic. According to the discussed merit of the circuit's symmetry, two similar parallel harmonic rejection networks are put in both branches of the power divider. Fig.9 shows the impedance of this network, and Fig.10 depicts that there is no considerable amount of higher-order harmonics in the output signal degrading the efficiency. Fig.11 indicates the proposed CCML based DPA's layout, and Table 2 makes a comparison among this work and the other recent GaAs pHEMT technology-based DPAs' performances.

Results
To model , out main Z change under the premise of modified load modulation, even in low-level power, the proposed DPA is designed in a two-stage structure. The main path has two 8×150 transistors. main PA 's first stage is biased in -1 v and 6.4 V for its gate and drain biases, respectively, and those of the second stages are -1 V and 7.4 V. Under the premise of CCLM, the auxiliary path enjoys four 8×150 two by two paralleled transistors. The first stage of aux PA has -1.4 V and 6.9 V for its gate and drain bias, while its second stage is biased in -1.2 V and 7.35 V for the bias of this stage's gate and drain, respectively. To make a comparison between a design with CCLM and another with the conventional load modulation, the results of these two DPAs in the same technology are provided in this paper, and it is concluded that for a technology in which , out main Z shows considerable power-based variation, revision of load modulation is needed. In this work, linear modeling of load modulation is viable, but designers should set premises proper for their own , out main Z trajectory. Results show that CCLM based circuit has the maximum PAE of 39.6%, maximum output power of 31.61dBm, at 8 GHz frequency. Those of the conventional load modulation based circuit are 28.3%, 30.12 dBm, at 8 GHz, respectively. Second harmonic rejection networks are put in both circuits, and there is no destructive amount of second harmonic signal in the output power of both designs, less than -50 dBm. were put in the input of both paths, and the amount of second harmonic signal in output power was checked; no significant amount of it was there.

Appendix
Amount of the elements of the Proposed DPA