Third International Workshop on Verification and Evaluation of Computer and Communication Systems (VECoS 2009) (VECOS)
Verification and Evaluation of Computer and Communication Systems (VECoS 2009)
2-3 July 2009
In this paper, we present a method to improve the testbench evaluation in a simulative verification process using formal properties. Assuming that at least for some part(s) of the design under test (DUT) a set of formal properties exists, the properties are transformed into a normalized form. The transformed properties, called microproperties, allow an objective evaluation of the testbench of the full DUT. It is possible to obtain more detailed coverage results using microproperties than by means of the original properties. This paper also describes how to obtain a unified metric from formal and non-formal verification results. Several examples including an AMBA AHB bus system are used to show the presented technique’s practical applications.