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System Level Design from HW/SW to Memory for Embedded Systems
other
Editor(s):
Marcelo Götz
,
Gunar Schirner
,
Marco Aurélio Wehrmeister
,
Mohammad Abdullah Al Faruque
,
Achim Rettberg
Publication date
(Print):
2017
Publisher:
Springer International Publishing
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There is no author summary for this book yet. Authors can add summaries to their books on ScienceOpen to make them more accessible to a non-specialist audience.
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Embodied Memory
Author and book information
Book
ISBN (Print):
978-3-319-90022-3
ISBN (Electronic):
978-3-319-90023-0
Publication date (Print):
2017
DOI:
10.1007/978-3-319-90023-0
SO-VID:
d71e4ae6-950e-45e0-bda5-2112ba6e00fc
License:
http://www.springer.com/tdm
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Book chapters
pp. 3
Ontological User Modeling for Ambient Assisted Living Service Personalization
pp. 15
Multi-Agent Based Implementation of an Embedded Image Processing System in FPGA for Precision Agriculture Using UAVs
pp. 27
Combining Service-Oriented Computing with Embedded Systems - A Robotics Case Study
pp. 38
Integration of Robot Operating System and Ptolemy for Design of Real-Time Multi-robots Environments
pp. 51
Bit-Precise Formal Verification for SystemC Using Satisfiability Modulo Theories Solving
pp. 64
Timed Path Conditions in MATLAB/Simulink
pp. 77
Structural Contracts – Motivating Contracts to Ensure Extra-Functional Semantics
pp. 88
Combining an Iterative State-Based Timing Analysis with a Refinement Checking Technique
pp. 103
Hierarchical Multicore-Scheduling for Virtualization of Dependent Real-Time Systems
pp. 116
Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs
pp. 128
Modeling and Analysis of SLDL-Captured NoC Abstractions
pp. 145
Taming the Memory Demand Complexity of Adaptive Vision Algorithms
pp. 159
HMC and DDR Performance Trade-offs
pp. 172
Managing Cache Memory Resources in Adaptive Many-Core Systems
pp. 185
A UML Profile to Couple the Production Code Generator TargetLink with UML Design Tools
pp. 197
Rapid, High-Level Performance Estimation for DSE Using Calibrated Weight Tables
pp. 210
Low Latency FPGA Implementation of Izhikevich-Neuron Model
pp. 218
Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays
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