A Survey of Techniques for Architecting Processor Components Using Domain-Wall Memory

Recent developments in the controlled movement of domain walls in magnetic nanowires by short pulses of spin-polarized current give promise of a nonvolatile memory device with the high performance and reliability of conventional solid-state memory but at the low cost of conventional magnetic disk drive storage. The racetrack memory described in this review comprises an array of magnetic nanowires arranged horizontally or vertically on a silicon chip. Individual spintronic reading and writing nanodevices are used to modify or read a train of approximately 10 to 100 domain walls, which store a series of data bits in each nanowire. This racetrack memory is an example of the move toward innately three-dimensional microelectronic devices.