Second International Workshop on Verification and Evaluation of Computer and Communication Systems (VECoS 2008) (VECoS)
Verification and Evaluation of Computer and Communication Systems
2 - 3 July 2008
In this paper, a new method to evaluate the response time in switched Ethernet automation architectures is developed. It is based on the modeling of the whole system in the form of timed event graphs and on the resulting state representation in Max-Plus algebra. After the resolution of the state equations and their fusion according to the working of the system, we obtained an algorithm giving the reaction delay of the architecture. With deep analysis of these equations we got to analytical formulas for direct calculus of the response time as a function of the features of the architecture. The minimal and maximal bounds of response time are also calculated. To check the validity of the results, simulations of the algorithm and experimental measurements on a laboratory platform are used. Finally, a comparison with results obtained using a classical method, shows the interest and the effectiveness of this new approach.