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      Æthereal Network on Chip:Concepts, Architectures, and Implementations

      Author(s): , ,
      Publication date Created:
      Publication date (Print):
      Journal: IEEE Design and Test of Computers
      Publisher: Institute of Electrical and Electronics Engineers (IEEE)

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          Networks on chips: a new SoC paradigm

          G. De Micheli, L Benini (2002)
          Article 0 comments Cited 139 times – based on 0 reviews     Review now
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            Synchronous data flow

            E.A. Lee, D.G. Messerschmitt (1987)
            Article 0 comments Cited 85 times – based on 0 reviews     Review now
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              Service disciplines for guaranteed performance service in packet-switching networks

              Hui Zhang (1995)
              Article 0 comments Cited 67 times – based on 0 reviews     Review now
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                Author and article information

                Journal
                Title: IEEE Design and Test of Computers
                Abbreviated Title: IEEE Des. Test. Comput.
                Publisher: Institute of Electrical and Electronics Engineers (IEEE)
                ISSN (Print): 0740-7475
                Publication date Created: May 2005
                Publication date (Print): May 2005
                Volume: 22
                Issue: 5
                Pages: 414-421
                Article
                DOI: 10.1109/MDT.2005.99
                SO-VID: 81ccd1e7-894a-49dd-aeb7-fdc5c64ca540
                Copyright © © 2005
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