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      An Ultra-Area-Efficient 1024-Point In-Memory FFT Processor

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          Abstract

          Current computation architectures rely on more processor-centric design principles. On the other hand, the inevitable increase in the amount of data that applications need forces researchers to design novel processor architectures that are more data-centric. By following this principle, this study proposes an area-efficient Fast Fourier Transform (FFT) processor through in-memory computing. The proposed architecture occupies the smallest footprint of around 0.1 mm 2 inside its class together with acceptable power efficiency. According to the results, the processor exhibits the highest area efficiency ( FFT / s / area ) among the existing FFT processors in the current literature.

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          Most cited references46

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          In-memory computing with resistive switching devices

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            RARE imaging: a fast imaging method for clinical MR.

            Based on the principles of echo imaging, we present a method to acquire sufficient data for a 256 X 256 image in from 2 to 40 s. The image contrast is dominated by the transverse relaxation time T2. Sampling all projections for 2D FT image reconstruction in one (or a few) echo trains leads to image artifacts due to the different T2 weighting of the echo. These artifacts cannot be described by a simple smearing out of the image in the phase direction. Proper distribution of the phase-encoding steps on the echoes can be used to minimize artifacts and even lead to resolution enhancement. In spite of the short data acquisition times, the signal amplitudes of structures with long T2 are nearly the same as those in a conventional 2D FT experiment. Our method, therefore, is an ideal screening technique for lesions with long T2.
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              Spin-transfer torque magnetic random access memory (STT-MRAM)

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                Author and article information

                Journal
                Micromachines (Basel)
                Micromachines (Basel)
                micromachines
                Micromachines
                MDPI
                2072-666X
                31 July 2019
                August 2019
                : 10
                : 8
                : 509
                Affiliations
                [1 ]Sensors Lab, Advanced Membranes & Porous Materials Center (AMPMC), Computer, Electrical and Mathematical Sciences and Engineering Division, King Abdullah University of Science and Technology (KAUST), Thuwal 23955-6900, Saudi Arabia
                [2 ]Center for Embedded and Cyber-physical Systems, University of California, Irvine, CA 92697, USA
                Author notes
                Author information
                https://orcid.org/0000-0002-0096-0365
                https://orcid.org/0000-0003-2410-7315
                https://orcid.org/0000-0003-1849-083X
                https://orcid.org/0000-0002-6982-365X
                https://orcid.org/0000-0001-7742-1282
                Article
                micromachines-10-00509
                10.3390/mi10080509
                6722736
                31370261
                8597002e-0e1c-496b-a94a-eb6033f5d892
                © 2019 by the authors.

                Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license ( http://creativecommons.org/licenses/by/4.0/).

                History
                : 30 June 2019
                : 30 July 2019
                Categories
                Article

                fast fourier transform,in-memory computing,associative processor,non-von neumann architecture

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