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      Diseño de Circuitos Digitales a Nivel de Registro empleando Diagramas ASM++ Translated title: Digital Circuit Design at Register Transfer Level using ASM++ Charts

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          Abstract

          Este artículo muestra la estrecha relación que existe entre los diagramas de estado algorítmicos (ASM charts) y los modernos lenguajes de descripción de circuitos, ambos empleados en el diseño de circuitos digitales. Se proponen sustanciales mejoras sobre la notación actual con el objetivo de desarrollar un compilador capaz de procesar automáticamente estos diagramas y generar el código VHDL o Verilog correspondiente. El uso de esta metodología facilita el aprendizaje del diseño de circuitos digitales a nivel de transferencia entre registros (RTL). El lenguaje gráfico propuesto es fácil de aprender y es entendido sin dificultad por estudiantes universitarios, quienes lo emplean como parte de la metodología de diseño para producir circuitos digitales sobre dispositivos reconfigurables tipo FPGA y CPLD.

          Translated abstract

          This article shows the close relationship between Algorithmic State Machines (ASM charts) and modern hardware description languages, both applied to digital electronic design. Important improvements on current notation have been proposed in order to develop a compiler capable of processing these charts and generating VHDL or Verilog code automatically, The use of this methodology facilitates the learning of electronic design at the register transfer level (RTL). The language proposed is easy to learn and comprehend with no much difficulty by university students who used it as part of design methodology to produce digital circuits on reconfigurable devices of the type FPGA and CPLD.

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          The design-methods comparison project

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            Designing Logic Systems using State Machines

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              Synthesis and Optimization of Pipelined Packet Processors

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                Author and article information

                Journal
                infotec
                Información tecnológica
                Inf. tecnol.
                Centro de Información Tecnológica (La Serena, , Chile )
                0718-0764
                2010
                : 21
                : 2
                : 91-102
                Affiliations
                [02] Valladolid orgnameUniversidad Europea Miguel de Cervantes España sanpab@ 123456eis.uva.es
                [01] Valladolid orgnameUniversidad de Valladolid orgdiv1Escuela de Ingenierías Industriales orgdiv2Departamento de Tecnología Electrónica España
                Article
                S0718-07642010000200012 S0718-0764(10)02100212
                10.4067/S0718-07642010000200012
                d9a1e71c-7caf-49a2-81f3-a6bf2c13a4a8

                This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.

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                Page count
                Figures: 0, Tables: 0, Equations: 0, References: 20, Pages: 12
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                SciELO Chile

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                metodología de diseño,compilador,gráficos ASM,register transfer level,nivel de transferencia de registro,design methodology,compiler,ASM charts,description languages,lenguajes de descripción

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