Improved resistive switching characteristics in Ni/SiNx/p++-Si devices by tuning x

Neuromorphic computing is an attractive computation paradigm that complements the von Neumann architecture. The salient features of neuromorphic computing are massive parallelism, adaptivity to the complex input information, and tolerance to errors. As one of the most crucial components in a neuromorphic system, the electronic synapse requires high device integration density and low-energy consumption. Oxide-based resistive switching devices have been shown to be a promising candidate to realize the functions of the synapse. However, the intrinsic variation increases significantly with the reduced spike energy due to the reduced number of oxygen vacancies in the conductive filament region. The large resistance variation may degrade the accuracy of neuromorphic computation. In this work, we develop an oxide-based electronic synapse to suppress the degradation caused by the intrinsic resistance variation. The synapse utilizes a three-dimensional vertical structure including several parallel oxide-based resistive switching devices on the same nanopillar. The fabricated three-dimensional electronic synapse exhibits the potential for low fabrication cost, high integration density, and excellent performances, such as low training energy per spike, gradual resistance transition under identical pulse training scheme, and good repeatability. A pattern recognition computation is simulated based on a well-known neuromorphic visual system to quantify the feasibility of the three-dimensional vertical structured synapse for the application of neuromorphic computation systems. The simulation results show significantly improved recognition accuracy from 65 to 90% after introducing the three-dimensional synapses.

Filamentary-based oxide resistive memory is considered as a disruptive technology for nonvolatile data storage and reconfigurable logic. Currently accepted models explain the resistive switching in these devices through the presence/absence of a conductive filament (CF) that is described as a reversible nanosized valence-change in an oxide material. During device operation, the CF cycles billion of times at subnanosecond speed, using few tens of microamperes as operating current and thus determines the whole device's performance. Despite its importance, the CF observation is hampered by the small filament size and its minimal compositional difference with the surrounding material. Here we show an experimental solution to this problem and provide the three-dimensional (3D) characterization of the CF in a scaled device. For this purpose we have recently developed a tomography technique which combines the high spatial resolution of scanning probe microscopy with subnanometer precision in material removal, leading to a true 3D-probing metrology concept. We locate and characterize in three-dimensions the nanometric volume of the conductive filament in state-of-the-art bipolar oxide-based devices. Our measurements demonstrate that the switching occurs through the formation of a single conductive filament. The filaments exhibit sizes below 10 nm and present a constriction near the oxygen-inert electrode. Finally, different atomic-size contacts are observed as a function of the programming current, providing evidence for the filament's nature as a defects modulated quantum contact.

Memristors are promising building blocks for the next-generation memory and neuromorphic computing systems. Most memristors use materials that are incompatible with the silicon dominant complementary metal-oxide-semiconductor technology, and require external selectors in order for large memristor arrays to function properly. Here we demonstrate a fully foundry-compatible, all-silicon-based and self-rectifying memristor that negates the need for external selectors in large arrays. With a p-Si/SiO2/n-Si structure, our memristor exhibits repeatable unipolar resistance switching behaviour (105 rectifying ratio, 104 ON/OFF) and excellent retention at 300 °C. We further build three-dimensinal crossbar arrays (up to five layers of 100 nm memristors) using fluid-supported silicon membranes, and experimentally confirm the successful suppression of both intra- and inter-layer sneak path currents through the built-in diodes. The current work opens up opportunities for low-cost mass production of three-dimensional memristor arrays on large silicon and flexible substrates without increasing circuit complexity.