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A 1.75GHz/3V DualModulus Divideby128/129 Prescaler in 0.7m CMOS
edited_book
Publication date:
2 2009
Publisher:
IEEE
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Book Chapter
Publication date:
2 2009
DOI:
10.1109/9780470545492.ch41
SO-VID:
d25a35b2-3dfa-4f06-8ad5-e71341fcf720
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Book chapters
LowPower Dividerless Frequency Synthesis Using Aperture Phase Detection
A 1.2 GHz CMOS DualModulus Prescaler Using New Dynamic DType FlipFlops
DeltaSigma FractionalN PhaseLocked Loops
Tail Current Noise Suppression in RF CMOS VCOs
A CMOS Frequency Synthesizer with an InjectionLocked Frequency Divider for a 5GHz Wireless LAN Receiver
Substrate Noise Coupling through Planar Spiral Inductor
Designing BangBang PLLs for Clock and Data Recovery in Serial Data Transmission Systems
A Simple Precharged CMOS Phase Frequency Detector
35GHz Static and 48GHz Dynamic Frequency Divider IC's Using 0.2m AlGaAs/GaAsHEMT's
Rotary TravelingWave Oscillator Arrays: A New Clock Technology
A 10Gb/s CMOS Clock and Data Recovery Circuit with Frequency Detection
A LowJitter WideRange SkewCalibrated DualLoop DLL Using Antifuse Circuitry for HighSpeed DRAM
A 2V 900MHz Monolithic CMOS DualLoop Frequency Synthesizer for GSM Receivers
RF Synthesis
A Fully Integrated SiGe Receiver IC for 10Gb/s Data Rate
Building Blocks
The Effect of Varactor Nonlinearity on the Phase Noise of Completely Integrated VCOs
Predicting the Phase Noise and Jitter of PLLBased Frequency Synthesizers
LowJitter ProcessIndependent DLL and PLL Based on SelfBiased Techniques
A Modeling Approach for ¿¿ FractionalN Frequency Synthesizers Allowing Straightforward Noise Analysis
A 1.8GHz SelfCalibrated PhaseLocked Loop with Precise I/Q Matching
Design of HighQ Varactors for LowPower Wireless Applications Using a Standard CMOS Process
A 10Gb/s CDR/DEMUX with LC Delay Line VCO in 0.18m CMOS
HighSpeed Architecture for a Programmable Frequency Divider and a DualModulus Prescaler
Devices and Circuits for PhaseLocked Systems
Clock Generation by PLLs and DLLs
An Adaptive PLL Tuning System Architecture Combining High Spectral Purity and Fast Settling Time
A 10Gb/s CMOS Clock and Data Recovery Circuit with a HalfRate Linear Phase Detector
A Low Jitter 0.3165 MHz CMOS PLL Frequency Synthesizer for 3 V/5 V Operation
Analysis and Design of an Optimally Coupled 5GHz Quadrature LC Oscillator
The Modeling, Characterization, and Design of Monolithic Inductors for Silicon RF IC's
Frontmatter
A Semidigital Dual DelayLocked Loop
Fast Switching Frequency Synthesizer with a DiscriminatorAided Phase Detector
A 1.5V 86mW/ch 8Channel 6223125Mb/s/ch CMOS SerDes Macrocell with Selectable Mul/Demul Ratio
Devices
A 1.75GHz/3V DualModulus Divideby128/129 Prescaler in 0.7m CMOS
A Stabilization Technique for PhaseLocked Frequency Synthesizers
A 2.5Gb/s Clock and Data Recovery IC with Tunable Jitter Characteristics for Use in LAN's and WAN's
A Fully Integrated CMOS Frequency Synthesizer with ChargeAveraging Charge Pump and DualPath Loop Filter for PCS and CellularCDMA Wireless Systems
A Study of Phase Noise in CMOS Oscillators
A 0.5m CMOS 4.0Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling
A 1.57GHz Fully Integrated Very LowPhaseNoise Quadrature VCO
Temperature Dependence of Q and Inductance in Spiral Inductors Fabricated in a SiliconGennanium/BiCMOS Technology
Measurements and Analysis of PLL Jitter Caused by Digital Switching Noise
PhysicsBased ClosedForm Inductance Expression for Compact Modeling of Integrated Spiral Inductors
A Portable Digital DLL for HighSpeed CMOS Interface Circuits
OnChip Spiral Inductors with Patterned Ground Shields for SiBased RF IC^apos;s
A LowJitter PLL Clock Generator for Microprocessors with Lock Range of 340612 MHz
Clock and Data Recovery IC for 40Gb/s FiberOptic Receiver
On the Use of MOS Varactors in RF VCO's
Phase Noise and Jitter
Active GHz Clock Network Using Distributed PLLs
A Fully Integrated 40Gb/s Clock and Data Recovery IC With 1:4 DEMUX in SiGe Technology
Analysis, Design, and Optimization of Spiral Inductors and Transformers for Si RF I's
DelayLocked Loops An Overview
A Family of LowPower Truly Modular Programmable Dividers in Standard 0.35m CMOS Technology
The Effects of a Ground Shield on the Characteristics and Performance of Spiral Inductors
A 40Gb/s Integrated Clock and Data Recovery Circuit in a 50GHz fT Silicon Bipolar Technology
A 27mW CMOS FractionalN Synthesizer Using Digital Compensation for 2.5Mb/s GFSK Modulation
A Study of Oscillator Jitter Due to Supply and Substrate Noise
Clock/Data Recovery PLL Using HalfFrequency Clock
CMOS DLLBased 2V 3.2ps Jitter 1GHz Clock Synthesizer and TemperatureCompensated Tunable Oscillator
A 21600MHz CMOS Clock Recovery PLL with LowVdd Capability
Jitter in Ring Oscillators
A WideRange DelayLocked Loop with a Fixed Latency of One Clock Cycle
Index
A LowNoise FastLock PhaseLocked Loop with Adaptive Bandwidth Control
Phase Noise in LC Oscillators
An Integrated 10/5GHz Injectionlocked Quadrature LC VCO in a 0.18m digital CMOS process
A 960Mb/s/pin Interface for SkewTolerant Bus Using Low Jitter PLL
Clock and Data Recovery
OnChip Measurement of the Jitter Transfer Function of ChargePump PhaseLocked Loops
A General Theory of Phase Noise in Electrical Oscillators
A RegisterControlled Symmetrical DLL for DoubleDataRate DRAM
Jitter and Phase Noise in Ring Oscillators
A Fully Integrated veo at 2 GHz
Original Contributions
A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for Microprocessor Clock Generation
A QFactor Enhancement Technique for Mmic Inductors
Physical Processes of Phase Noise in Differential LC Oscillators
A 1.6GHz Dual Modulus Prescaler Using the Extended TrueSinglePhaseClock CMOS Circuit Technique (ETSPC)
A LowNoise, LowPower VCO with Automatic Amplitude Control for Wireless Applications
Superharmonic InjectionLocked Frequency Dividers
A CMOS Monolothic ¿¿Controlled FractionalN Frequency Synthesizer for DSC1800
A LowPhaseNoise 5GHz Quadrature CMOS VCO using CommonMode Inductive Coupling
LowPower LowPhaseNoise Differentially Tuned Quadrature VCO Design in Standard CMOS
LowNoise VoltageControlled Oscillators Using Enhanced LCTanks
A DualLoop DelayLocked Loop Using Multiple VoltageControlled Delay Lines
A 2.6GHz/5.2GHz Frequency Synthesizer in 0.4m CMOS Technology
A LowJitter 1251250MHz ProcessIndependent and RipplePoleless 0.18m CMOS PLL Based on a SampleReset Loop Filter
SiGe Clock and Data Recovery IC with LinearType PLL for 10Gb/s SONET Application
Estimation Methods for Quality Factors of Inductors Fabricated in Silicon Integrated Circuit Process Technologies
An AllAnalog Multiphase DelayLocked Loop Using a Replica Delay Line for WideRange Operation and LowJitter Performance
A 1.1GHz CMOS FractionalN Frequency Synthesizer with a 3b ThirdOrder ¿¿ Modulator
Stacked Inductors and Transformers in CMOS Technology
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