Hi-MNOS II technology for a 64-kbit byte-erasable 5-V-only EEPROM

Katto, H.; Uchida, K.; Terasawa, M; Hagiwara, T; Yasui, T; Minami, S.; Nabetani, S; Yatsuda, Y.

doi:10.1109/T-ED.1985.21933

Record: found
Abstract: not found
Article: not found

Hi-MNOS II technology for a 64-kbit byte-erasable 5-V-only EEPROM

Author(s): Y. Yatsuda , S. Nabetani , K. Uchida , S. Minami , M. Terasawa , T. Hagiwara , H. Katto , T. Yasui

Publication date (Print): February 1985

Journal: IEEE Transactions on Electron Devices

Publisher: Institute of Electrical and Electronics Engineers (IEEE)

Read this article at

ScienceOpenPublisher

Bookmark

There is no author summary for this article yet. Authors can add summaries to their articles on ScienceOpen to make them more accessible to a non-specialist audience.

Related collections

Author and article information

Journal

Title: IEEE Transactions on Electron Devices

Abbreviated Title: IEEE Trans. Electron Devices

Publisher: Institute of Electrical and Electronics Engineers (IEEE)

ISSN (Print): 0018-9383

Publication date Created: February 1985

Publication date (Print): February 1985

Volume: 32

Issue: 2

Pages: 224-231

Article

DOI: 10.1109/T-ED.1985.21933

SO-VID: 36579a48-a2d9-448e-916c-02b8a4eae554

History

Data availability:

Hi-MNOS II technology for a 64-kbit byte-erasable 5-V-only EEPROM

Read this article at

Related collections

Technology, Mind, and Behavior

Author and article information

Journal

Article

History

Comments

Comment on this article

Similar content 3,260

Cited by 5