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      Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability

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          Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits

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            Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits

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              Author and article information

              Journal
              IEEE Transactions on Computers
              IEEE Trans. Comput.
              Institute of Electrical and Electronics Engineers (IEEE)
              0018-9340
              June 1980
              June 1980
              : C-29
              : 6
              : 527-531
              Article
              10.1109/TC.1980.1675614
              6036076e-8e48-4581-9db1-eb87c4e6c48d
              © 1980
              History

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