A 28.5 GB/s CMOS non-blocking router for terabit/s connectivity between multiple processors and peripheral I/O nodes

Nair, R; Borkar, N.Y.; Browning, C.S.; Dermer, G.E.; Eriaguntla, V.; Govindarajulu, V.; Pangal, A.; Prijic, J.D.; Rankin, L.; Seligman, E.; Vangal, S.; Wilson, H.A.

doi:10.1109/ISSCC.2001.912614

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A 28.5 GB/s CMOS non-blocking router for terabit/s connectivity between multiple processors and peripheral I/O nodes

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Author(s): R. Nair , N.Y. Borkar , C.S. Browning , G.E. Dermer , V. Eriaguntla , V. Govindarajulu , A. Pangal , J.D. Prijic , L. Rankin , E. Seligman , S. Vangal , H.A. Wilson

Publication date: 2001

Publisher: IEEE

Conference name: 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (ISSCC-01)

Conference date: 5-7 Feb. 2001

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Publisher: IEEE

Publication date: 2001

Pages: 224-225,

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DOI: 10.1109/ISSCC.2001.912614

SO-VID: 633aaf09-bfc5-4f0c-bf37-1b6328bee309

Conference name: 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

Conference acronym: ISSCC-01

Conference location: San Francisco, CA, USA

Conference date: 5-7 Feb. 2001

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A 28.5 GB/s CMOS non-blocking router for terabit/s connectivity between multiple processors and peripheral I/O nodes

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