A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture

Kubota, M; Akamatsu, H.; Matsushima, J; Fujiwara, A; Yamauchi, H; Kotani, H; Yamada, T; Inoue, M; Aoi, N; Fuse, G; Ogawa, S; Odanaka, S.; Ueno, A; Yamamoto, H; Nakao, I; Fukumoto, M

doi:10.1109/4.5931

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A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture

Author(s): M. Inoue , T. Yamada , H. Kotani , H. Yamauchi , A. Fujiwara , J. Matsushima , H. Akamatsu , M. Fukumoto , M. Kubota , I. Nakao , N. Aoi , G. Fuse , S. Ogawa , S. Odanaka , A. Ueno , H. Yamamoto

Publication date (Print): Oct. 1988

Journal: IEEE Journal of Solid-State Circuits

Publisher: Institute of Electrical and Electronics Engineers (IEEE)

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Circuit technologies for 16Mb DRAMs

J Yamada, T. Mano, T. Matsumura … (2024)

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A substrate-plate trench-capacitor (SPT) memory cell for dynamic RAM's

R.L. Mohler, B.J. Machesney, T.H. Ning … (1986)

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A 16mb Dram with an Open Bit-Line Architecture

Yamamoto, Aoi, Fuse … (1988)

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Title: IEEE Journal of Solid-State Circuits

Abbreviated Title: IEEE J. Solid-State Circuits

Publisher: Institute of Electrical and Electronics Engineers (IEEE)

ISSN (Print): 00189200

Publication date (Print): Oct. 1988

Volume: 23

Issue: 5

Pages: 1104-1112

Article

DOI: 10.1109/4.5931

SO-VID: df849747-51f4-4122-a98a-507dc283abc5

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A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture

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Higher order chromatin architecture

Most cited references 15

Circuit technologies for 16Mb DRAMs

A substrate-plate trench-capacitor (SPT) memory cell for dynamic RAM's

A 16mb Dram with an Open Bit-Line Architecture

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