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      Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC

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          Lower-current and fast switching of a perpendicular TMR for high speed and high density spin-transfer-torque MRAM

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            A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory

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              CACTI: an enhanced cache access and cycle time model

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                Author and article information

                Journal
                IEEE Transactions on Very Large Scale Integration (VLSI) Systems
                IEEE Trans. VLSI Syst.
                Institute of Electrical and Electronics Engineers (IEEE)
                1063-8210
                1557-9999
                October 2016
                October 2016
                : 24
                : 10
                : 3041-3054
                10.1109/TVLSI.2016.2536747
                © 2016
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