Verifying SystemC with Scenario

This paper proposes a new approach for the analysis and verification of complex systems. The core of the method consists in combining model-checking and abstract interpretation for analysis and verification. The system is modeled by a Labeled Transition System obtained from a SystemC description, and the properties to be verified are formalized as an observer automaton with assertions. To ease the specification of properties, we introduce a dedicated language, named Scenario. The contributions of the paper are twofold: the language for describing the expected properties and behavior of a system as Scenario, and a static analysis for verifying such properties.