Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors

Lo, G. Q.; Balasubramanian, N; Kwong, D.-L.; Fang, W. W.; Singh, N.; Bera, L K; Rustagi, S. C.; Nguyen, H. S.

doi:10.1109/LED.2007.891268

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Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors

Author(s): W. W. Fang , N. Singh , L. K. Bera , H. S. Nguyen , S. C. Rustagi , G. Q. Lo , N. Balasubramanian , D.-L. Kwong

Publication date (Print): March 2007

Journal: IEEE Electron Device Letters

Publisher: Institute of Electrical and Electronics Engineers (IEEE)

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SEMICONDUCTOR NANOWIRES AND NANOTUBES

Matt Law, Joshua E. Goldberger, Peidong Yang (2004)

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General Synthesis of Compound Semiconductor Nanowires

X. Duan, C. Lieber (2000)

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Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor Applications

R Chau, S Datta, M. Doczy … (2005)

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Journal

Title: IEEE Electron Device Letters

Abbreviated Title: IEEE Electron Device Lett.

Publisher: Institute of Electrical and Electronics Engineers (IEEE)

ISSN (Print): 0741-3106

Publication date Created: March 2007

Publication date (Print): March 2007

Volume: 28

Issue: 3

Pages: 211-213

Article

DOI: 10.1109/LED.2007.891268

SO-VID: 6a128e50-aad8-4a4f-97ab-02885a3a67a0

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Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors

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Electron Channelling Contrast Imaging (ECCI)

Most cited references 12

SEMICONDUCTOR NANOWIRES AND NANOTUBES

General Synthesis of Compound Semiconductor Nanowires

Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor Applications

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