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      Voltage divider effect for the improvement of variability and endurance of TaO x memristor

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          Abstract

          The impact of a series resistor (R S) on the variability and endurance performance of memristor was studied in the TaO x memristive system. A dynamic voltage divider between the R S and memristor during both the set and the reset switching cycles can suppress the inherent irregularity of the voltage dropped on the memristor, resulting in a greatly reduced switching variability. By selecting the proper resistance value of R S for the set and reset cycles respectively, we observed a dramatically improved endurance of the TaO x memristor. Such a voltage divider effect can thus be critical for the memristor applications that require low variability, high endurance and fast speed.

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          Nanoscale memristor device as synapse in neuromorphic systems.

          A memristor is a two-terminal electronic device whose conductance can be precisely modulated by charge or flux through it. Here we experimentally demonstrate a nanoscale silicon-based memristor device and show that a hybrid system composed of complementary metal-oxide semiconductor neurons and memristor synapses can support important synaptic functions such as spike timing dependent plasticity. Using memristors as synapses in neuromorphic circuits can potentially offer both high connectivity and high density required for efficient computing.
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            A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O(5-x)/TaO(2-x) bilayer structures.

            Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaO(x)-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 10(12). Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.
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              Fully room-temperature-fabricated nonvolatile resistive memory for ultrafast and high-density memory application.

              Through a simple industrialized technique which was completely fulfilled at room temperature, we have developed a kind of promising nonvolatile resistive switching memory consisting of Ag/ZnO:Mn/Pt with ultrafast programming speed of 5 ns, an ultrahigh R(OFF)/R(ON) ratio of 10(7), long retention time of more than 10(7) s, good endurance, and high reliability at elevated temperatures. Furthermore, we have successfully captured clear visualization of nanoscale Ag bridges penetrating through the storage medium, which could account for the high conductivity in the ON-state device. A model concerning redox reaction mediated formation and rupture of Ag bridges is therefore suggested to explain the memory effect. The Ag/ZnO:Mn/Pt device represents an ultrafast and highly scalable (down to sub-100-nm range) memory element for developing next generation nonvolatile memories.
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                Author and article information

                Journal
                Sci Rep
                Sci Rep
                Scientific Reports
                Nature Publishing Group
                2045-2322
                02 February 2016
                2016
                : 6
                : 20085
                Affiliations
                [1 ]Hewlett Packard Labs, Hewlett Packard Enterprise , Palo Alto, California 94304, USA
                Author notes
                [*]

                Present Address: The Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA 01003, USA.

                Article
                srep20085
                10.1038/srep20085
                4735717
                26830763
                8194c586-a99d-4c19-83fb-2bd9b6ee7888
                Copyright © 2016, Macmillan Publishers Limited

                This work is licensed under a Creative Commons Attribution 4.0 International License. The images or other third party material in this article are included in the article’s Creative Commons license, unless indicated otherwise in the credit line; if the material is not included under the Creative Commons license, users will need to obtain permission from the license holder to reproduce the material. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/

                History
                : 09 October 2015
                : 15 December 2015
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