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      Iddq testing for CMOS VLSI

      Proceedings of the IEEE
      Institute of Electrical and Electronics Engineers (IEEE)

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          Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits

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            Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability

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              On physical models for gate oxide breakdown

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                Author and article information

                Journal
                Proceedings of the IEEE
                Proc. IEEE
                Institute of Electrical and Electronics Engineers (IEEE)
                0018-9219
                1558-2256
                April 2000
                April 2000
                : 88
                : 4
                : 544-568
                Article
                10.1109/5.843000
                cc8a3598-7254-49dd-ae0d-ed555c40f114
                © 2000
                History

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