Parallel 2D FFT implementation on FPGA suitable for real-time MR image processing

Abstract

We report the design and implementation of a parallel two-dimensional fast Fourier transform (2D FFT) algorithm on a Field Programmable Gate Array (FPGA) for real-time MR image processing. Although a number of architectures of 2D FFT hardware processors have been reported, these generic processors or IP cores are not always effective for processing MRI data. The key feature of our design is that our processors are customized solely for real-time MRI applications. We demonstrate that by considering the unique features of real-time MRI data streams, we were able to develop and implement the 2D FFT processors that are resource-efficient and flexible enough to handle both regular and irregular data. Using a data-driven approach, we were able to simplify the inter-processor data communication while maintaining data synchronization without a synchronous clock signal bus and complex interconnection network. We experimentally verified our designs by processing multi-slice image data sets with 128 × 128 and 256 × 256 in-plane resolution. The results demonstrate the effectiveness of our 2D FFT processors and show that image reconstruction can be accelerated in proportion to the parallel processing factor. We achieved image-reconstruction processing rates up to 3000 and 800 slices per second for images with 128 × 128 and 256 × 256 in-plane resolution, respectively. The results also indicate that the image-reconstruction acceleration is primarily limited by the speed of the data transfer between the FPGA device and external sensors.