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      Optimized trench MOSFET technologies for power devices

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          Most cited references 26

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          Resistivity, mobility and impurity levels in GaAs, Ge, and Si at 300°K

           S.M. Sze,  J.C. Irvin (1968)
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            VLSI Process modeling—SUPREM III

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              Modeling of the on-resistance of LDMOS, VDMOS, and VMOS power transistors

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                Author and article information

                Journal
                IEEE Transactions on Electron Devices
                IEEE Trans. Electron Devices
                Institute of Electrical and Electronics Engineers (IEEE)
                00189383
                June 1992
                : 39
                : 6
                : 1435-1443
                Article
                10.1109/16.137324
                0f3a738d-da92-4d6d-b0d3-c4ce8df44e6c
                © 1992
                Product

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